# SipiSchFile 3.0
# Generated 2023-10-27 14:43:19.924294
SipiSchematic|Libname|EVB_mm_lib|Name|0900AD47A2450-EB1SMA|AnalysisType|7|AnalysisName|0900AD47A2450|SchematicType|2|LayoutLibName|EVB_mm_lib|LayoutCellName|0900AD47A2450-EB1SMA|LayoutViewName|layout|End
IOPort|1|Name|P1|Z|50.0|Port|P1|End
IOPort|2|Name|P2|Z|50.0|Port|P2|End
Var|1|Name|C_1p0pF_R1|Value|0|Name|C_1p0pF_L1|Value|0|Name|C_1p0pF_C1|Value|1e-12|End
CmpAnnotation|C_1p0pF|End
Component|3|Name|C1|Type|Lumped|Arrangement|Series:SRLC|R|var:C_1p0pF_R1|L|var:C_1p0pF_L1|C|var:C_1p0pF_C1|Port1|C1_P1_C1.P1_C1_P2_C1.P1|Enabled|TRUE|End
Var|2|Name|L_2p7nH_R2|Value|0|Name|L_2p7nH_L2|Value|2.7e-09|Name|L_2p7nH_C2|Value|0|End
CmpAnnotation|L_2p7nH|End
Component|4|Name|L1|Type|Lumped|Arrangement|Series:SRL|R|var:L_2p7nH_R2|L|var:L_2p7nH_L2|C|var:L_2p7nH_C2|Port1|L1_P1_C1.P1_L1_P2_P2|Enabled|TRUE|End
Var|3|Name|L_12nH_R3|Value|0|Name|L_12nH_L3|Value|1.2e-08|Name|L_12nH_C3|Value|0|End
CmpAnnotation|L_12nH|End
Component|5|Name|L2|Type|Lumped|Arrangement|Series:SRL|R|var:L_12nH_R3|L|var:L_12nH_L3|C|var:L_12nH_C3|Port1|L2_P1_L2.P1_L2_P2_P1|Enabled|TRUE|End
Var|4|Name|C_8p2pF_R4|Value|0|Name|C_8p2pF_L4|Value|0|Name|C_8p2pF_C4|Value|8.2e-12|End
CmpAnnotation|C_8p2pF|End
Component|6|Name|C2|Type|Lumped|Arrangement|Series:SRLC|R|var:C_8p2pF_R4|L|var:C_8p2pF_L4|C|var:C_8p2pF_C4|Port1|C2_P1_P1_C2_P2_C1.P1|Enabled|TRUE|End
Var|5|Name|L_5p1nH_R5|Value|0|Name|L_5p1nH_L5|Value|5.1e-09|Name|L_5p1nH_C5|Value|0|End
CmpAnnotation|L_5p1nH|End
Component|7|Name|L3|Type|Lumped|Arrangement|Series:SRL|R|var:L_5p1nH_R5|L|var:L_5p1nH_L5|C|var:L_5p1nH_C5|Port1|L3_P1_P1_L3_P2_C1.P1|Enabled|TRUE|End
Model|7|Name|0900AD47A2450|FileName|0900AD47A2450-EB1SMA_rfpro_0900AD47A2450.sio|FileType|SMatrixIO|LocationName|data|LocationType|relDir|Ports|7|Port1|+++
+++|P1|Port2|P2|Port3|C1_P1_C1.P1_C1_P2_C1.P1|Port4|L1_P1_C1.P1_L1_P2_P2|Port5|L2_P1_L2.P1_L2_P2_P1|Port6|C2_P1_P1_C2_P2_C1.P1|Port7|L3_P1_P1_L3_P2_C1.P1|+++
+++|End
AnalysisSettings|StartFreq|500.0 MHz|EndFreq|10.0 GHz|Dec|50|End